US 12,248,761 B2
Deterministic reset mechanism for asynchronous gearbox FIFOs for predictable latency
Riyas Noorudeen Remla, Singapore (SG); and Warren E. Cory, Redwood City, CA (US)
Assigned to XILINX, INC., San Jose, CA (US)
Filed by XILINX, INC., San Jose, CA (US)
Filed on Mar. 31, 2023, as Appl. No. 18/129,762.
Prior Publication US 2024/0329924 A1, Oct. 3, 2024
Int. Cl. G06F 5/06 (2006.01); G06F 1/10 (2006.01)
CPC G06F 5/06 (2013.01) [G06F 1/10 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method for deterministic de-assertion of write and read resets of an asynchronous gearbox FIFO having unequal write and read data bit widths, comprising:
providing first and second clocks that are harmonically related in frequency, the first clock having a first clock frequency and the second clock having a second clock frequency;
deriving a reset beacon waveform from the first clock;
deriving a third clock from the second clock, the third clock having a third clock frequency;
sampling first and second logic levels of the reset beacon waveform at the third clock frequency, while adjusting a phase of the third clock frequency;
observing cyclical behavior of the sampled first and second logic levels of the reset beacon waveform; and
if a change in the cyclical behavior of the sampled first and second logic levels of the reset beacon waveform is detected, then de-asserting a write reset and a read reset.