US 12,248,705 B2
Dynamic memory address write policy translation based on performance needs
Giuseppe Cariello, Boise, ID (US); and Jonathan Scott Parry, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 15, 2022, as Appl. No. 17/865,760.
Application 17/865,760 is a continuation of application No. 16/521,385, filed on Jul. 24, 2019, granted, now 11,435,944.
Prior Publication US 2022/0350539 A1, Nov. 3, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 12/06 (2006.01)
CPC G06F 3/0659 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 12/0646 (2013.01); G06F 2212/1016 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A device comprising:
at least one memory array configured on a plurality of dies; and
at least one processor configured to:
select a write policy of programming a plurality of pages of data to the at least one memory array, wherein the write policy is selected from a plurality of schemes including:
a first addressing scheme in which the plurality of pages are programmed on one of the plurality of dies sequentially one page after another; and
a second addressing scheme in which the plurality of pages are distributed to the plurality of dies for programming in parallel for the plurality of pages;
reserve a memory buffer according to the write policy selected to program the data into the memory array, wherein the memory buffer is of a first size for programming the data according to the first addressing scheme and of a second size different from the first size for programming the data according to the second addressing scheme; and
program the data, received from a host using the memory buffer, according to the write policy.