US 12,248,700 B2
Storage system utilizing transaction layer packet contained steering information
Hyeokjun Choe, Hwaseong-si (KR); Jeongho Lee, Gwacheon-si (KR); Younggeon Yoo, Seoul (KR); and Wonseb Jeong, Suwon-si (KR)
Assigned to Samsung Electronics Co., Ltd., (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Jun. 28, 2022, as Appl. No. 17/852,022.
Claims priority of application No. 10-2022-0023367 (KR), filed on Feb. 23, 2022.
Prior Publication US 2023/0266917 A1, Aug. 24, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A storage system comprising:
a host, wherein the host includes a host processor and a host memory buffer, wherein the host processor includes a central processing unit (CPU) core controlling operation of the host and includes a cache within the host processor, and the cache is dedicated to the CPU core, and wherein the host memory buffer includes a submission queue and a completion queue; and
a storage device connected to the host through a link, communicating with the host using a transaction layer packet (TLP), and including a nonvolatile memory device (NVM) and a storage controller controlling the NVM,
wherein the host is configured to write a nonvolatile memory express (NVMe) command indicating a destination to the submission queue,
wherein the storage controller is configured to read data from the NVM, directly access the cache in response to destination information associated with the destination, and store target data corresponding to data to be updated from among the read data in the cache,
wherein the storage controller includes:
a host interface connected to a physical layer of the host,
a command parser connected to the host interface, wherein the command parser is configured to generate the destination information by parsing the NVMe command,
a nonvolatile memory interface connected to the command parser and the NVM, wherein the nonvolatile memory interface is configured to read the data from the NVM by transmitting the NVMe command to the NVM, and
a first direct memory access (DMA) engine configured to receive the read data from the nonvolatile memory interface and receive the destination information from the command parser,
wherein the host interface is configured to receive the read data and the destination information from the first DMA engine, generate the TLP in response to the read data and the destination information, and transmit the TLP to the host through the link,
wherein the host further includes a root complex connected to the host processor and the host memory buffer,
wherein the root complex includes a second DMA engine, and
wherein the second DMA engine is configured to provide the target data to the cache and provide non-target data from among the read data, excepting the target data, to the host memory buffer in response to the destination information.