	US 12,248,696 B2
	Techniques to repurpose static random access memory rows to store a look-up-table for processor-in-memory operations
Saurabh Jain, Bengaluru (IN); Srivatsa Rangachar Srinivasa, Hillsboro, OR (US); Akshay Krishna Ramanathan, State College, PA (US); Gurpreet Singh Kalsi, Bangalore (IN); Kamlesh R. Pillai, Bangalore (IN); and Sreenivas Subramoney, Bangalore (IN)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 7, 2021, as Appl. No. 17/340,866.
Prior Publication US 2022/0391128 A1, Dec. 8, 2022
Int. Cl. G06F 3/06 (2006.01); G06F 7/523 (2006.01)

CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0673 (2013.01); G06F 7/523 (2013.01)]

25 Claims

1. A memory device comprising:

a plurality of static random access memory (SRAM) sub-arrays; and

a plurality of compute circuitry, individual compute circuitry from among the plurality of compute circuitry arranged to access data maintained in a corresponding SRAM sub-array from among the plurality of SRAM sub-arrays to enable the individual compute circuitry to execute a multiply and accumulate (MAC) operation, the plurality of SRAM sub-arrays to each include:

a first precharge circuitry to precharge bitlines coupled with all bit cell rows; and

a second precharge circuitry to precharge bitlines coupled with a portion of the bit cell rows,

wherein, responsive to a first signal received from a corresponding individual compute circuitry, the corresponding SRAM sub-array causes switches separately included in the corresponding SRAM sub-array to open respective bitline circuits to isolate the bitlines coupled with all bit cell rows from the bitlines coupled with the portion of bit cell rows, the portion of bit cell rows to store look up table (LUT) entries that include multiplication results and to store a configuration block that includes instructions for the corresponding individual compute circuitry to execute a MAC operation using the multiplication results in the LUT entries.