US 12,248,570 B2
Side-channel exploit detection
Paul Carlson, Santa Clara, CA (US); Rahuldeva Ghosh, Portland, OR (US); Baiju Patel, Portland, OR (US); and Zhong Chen, Santa Clara, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on May 9, 2022, as Appl. No. 17/739,930.
Application 17/739,930 is a continuation of application No. 16/233,810, filed on Dec. 27, 2018, granted, now 11,372,972.
Claims priority of provisional application 62/645,097, filed on Mar. 19, 2018.
Prior Publication US 2022/0335127 A1, Oct. 20, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 21/56 (2013.01); G06F 3/06 (2006.01); G06F 12/0802 (2016.01); G06F 21/62 (2013.01); G06F 21/75 (2013.01); G06N 20/00 (2019.01)
CPC G06F 21/56 (2013.01) [G06F 3/062 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 12/0802 (2013.01); G06F 21/6218 (2013.01); G06F 21/755 (2017.08); G06N 20/00 (2019.01); G06F 2212/68 (2013.01); G06F 2221/034 (2013.01)] 25 Claims
OG exemplary drawing
 
1. An apparatus comprising control circuitry to:
determine, for individual ones of a plurality of time intervals, a ratio based on a first value divided by a sum of the first value and a second value, wherein:
the first value corresponds to a number of central processing unit (CPU) cache misses over said individual ones of the plurality of time intervals; and
the second value corresponds to a number of dual/data translation lookaside buffer (DTLB) load misses over said individual ones of the plurality of time intervals;
identify, based on the ratio, a trend over the plurality of time intervals; and
responsive to an identification of a deviation in the trend, generate one or more output signals indicative of a side channel exploit execution.