US 12,248,567 B2
Row hammer interrupts to the operating system
Sujeet Ayyapureddi, Boise, ID (US); Tamara Schmitz, Boise, ID (US); Edmund Gieske, Boise, ID (US); Nicolo Izzo, Boise, ID (US); and Markus H. Geiger, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 8, 2022, as Appl. No. 17/940,785.
Claims priority of provisional application 63/301,993, filed on Jan. 21, 2022.
Prior Publication US 2023/0237152 A1, Jul. 27, 2023
Int. Cl. G06F 21/55 (2013.01); G06F 21/54 (2013.01)
CPC G06F 21/554 (2013.01) [G06F 21/54 (2013.01); G06F 21/556 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A device comprising:
a first interface configured to communicate with a host computing device;
a second interface configured to communicate with a memory media device;
a multi-layer detector including a row hammer detector for a memory controller and a row hammer detector for the memory media device that can be configured to perform simultaneous row hammer detection; and
a processing circuitry at least configured to:
implement a row hammer mitigation operation configured to:
detect, using the row hammer detector for the memory media device, a row hammer attack and the row hammer detector for the memory media device generates and transmits a signal that indicates detection of the row hammer attack;
receive at the memory controller the signal that indicates detection of the row hammer attack on the memory media device;
generate by the memory controller an interrupt in response to the signal that indicates the detection of the row hammer attack; and
communicate the interrupt to the host computing device.