US 12,248,564 B2
Systems and methods for transforming instructions for metadata processing
Steven Milburn, Cranston, RI (US); and Eli Boling, Manchester, MA (US)
Assigned to Dover Microsystems, Inc., Wayland, MA (US)
Filed by Dover Microsystems, Inc., Wayland, MA (US)
Filed on Apr. 2, 2024, as Appl. No. 18/625,085.
Application 18/625,085 is a continuation of application No. 16/966,863, previously published as PCT/US2019/016276, filed on Feb. 1, 2019.
Claims priority of provisional application 62/625,746, filed on Feb. 2, 2018.
Claims priority of provisional application 62/625,802, filed on Feb. 2, 2018.
Claims priority of provisional application 62/635,319, filed on Feb. 26, 2018.
Prior Publication US 2024/0394362 A1, Nov. 28, 2024
Int. Cl. G06F 21/54 (2013.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 21/12 (2013.01)
CPC G06F 21/54 (2013.01) [G06F 9/30058 (2013.01); G06F 9/30101 (2013.01); G06F 9/3017 (2013.01); G06F 9/3806 (2013.01); G06F 21/121 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A system comprising:
metadata processing hardware and at least one processor programed by executable instructions to process metadata, wherein the metadata processing hardware and the at least one programmed processor are configured to:
receive first instruction information associated with at least one first instruction executed by a host processor, wherein the at least one first instruction is part of a first instruction path;
use the first instruction information to obtain first metadata associated with the at least one first instruction;
use the first metadata to transform the first instruction information into second instruction information, wherein:
the second instruction information is associated a second instruction path;
an execution of the first instruction path and an execution of the second instruction path have a same effect on one or more hardware entities and one or more memory locations; and the second instruction path represents fewer operations than the first instruction path; and use second metadata associated with the second instruction information to determine whether the at least one first instruction is allowable for execution according to at least one policy; and in response to determining that the at least one first instruction is allowable, provide, to an interlock, an indication to release a queued result of executing the at least one first instruction for use by the system.