US 12,248,562 B2
Domain transition disable configuration parameter
Thomas Christopher Grocutt, Cambridge (GB)
Assigned to Arm Limited, Cambridge (GB)
Appl. No. 17/756,949
Filed by Arm Limited, Cambridge (GB)
PCT Filed Nov. 11, 2020, PCT No. PCT/GB2020/052855
§ 371(c)(1), (2) Date Jun. 6, 2022,
PCT Pub. No. WO2021/116654, PCT Pub. Date Jun. 17, 2021.
Claims priority of application No. 1918216 (GB), filed on Dec. 11, 2019.
Prior Publication US 2022/0366037 A1, Nov. 17, 2022
Int. Cl. G06F 21/54 (2013.01); G06F 9/30 (2018.01); G06F 9/32 (2018.01); G06F 9/38 (2018.01); G06F 21/55 (2013.01)
CPC G06F 21/54 (2013.01) [G06F 9/30054 (2013.01); G06F 9/30145 (2013.01); G06F 9/30189 (2013.01); G06F 9/323 (2023.08); G06F 9/38 (2013.01); G06F 9/3854 (2023.08); G06F 9/3861 (2013.01); G06F 21/554 (2013.01)] 24 Claims
OG exemplary drawing
 
1. An apparatus comprising:
processing circuitry configured to perform data processing in one of a plurality of security domains including at least a secure domain and a less secure domain;
memory access checking circuitry configured to check whether a memory access is allowed depending on a current security domain of the processing circuitry; and
a control storage location configured to store a domain transition disable configuration parameter specifying whether domain transitions between the secure domain and the less secure domain are enabled or disabled in at least one mode of the processing circuitry; in which:
in said at least one mode of the processing circuitry, when the domain transition disable configuration parameter specifies that said domain transitions are disabled in said at least one mode, the processing circuitry is configured to:
trigger signalling of a disabled domain transition fault in response to an attempt to transition from the secure domain to the less secure domain; and,
trigger signalling of the disabled domain transition fault in response to an attempt to transition from the less secure domain to the secure domain.