US 12,248,532 B2
Optimization processing unit utilizing digital oscillators
Jeffrey Chou, Boston, MA (US); Suraj Bramhavar, Arlington, MA (US); and Jeffrey G. Bernstein, Middleton, MA (US)
Assigned to Sync Computing Corp., Cambridge, MA (US)
Filed by Sync Computing Corp., Cambridge, MA (US)
Filed on Jul. 28, 2021, as Appl. No. 17/387,294.
Claims priority of provisional application 63/058,418, filed on Jul. 29, 2020.
Claims priority of provisional application 63/058,420, filed on Jul. 29, 2020.
Prior Publication US 2022/0035889 A1, Feb. 3, 2022
Int. Cl. G06F 17/13 (2006.01); G06F 13/36 (2006.01)
CPC G06F 17/13 (2013.01) [G06F 13/36 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A system, comprising:
a plurality of digital oscillators; and
at least one programmable interconnect configured to provide weights for and to selectably couple at least a portion of the plurality of digital oscillators,
wherein the plurality of digital oscillators and the at least one programmable interconnect form an optimization processing unit (OPU);
wherein the plurality of digital oscillators includes a plurality of injection locked digital oscillators, each of the plurality of the injection locked digital oscillators being a differential equation solver; and
wherein the differential equation solver is configured to solve at least one governing differential equation for a resistance-inductance-capacitance circuit.