US 12,248,516 B2
Flexible, scalable graph-processing accelerator
Ganesh Dasika, Austin, TX (US); Michael Ignatowski, Austin, TX (US); Michael J Schulte, Austin, TX (US); Gabriel H Loh, Bellevue, WA (US); Valentina Salapura, Santa Clara, CA (US); and Angela Beth Dalton, Austin, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Feb. 8, 2024, as Appl. No. 18/436,116.
Application 18/436,116 is a continuation of application No. 17/564,413, filed on Dec. 29, 2021, granted, now 11,921,784.
Claims priority of provisional application 63/188,175, filed on May 13, 2021.
Prior Publication US 2024/0419735 A1, Dec. 19, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 15/80 (2006.01); G06F 16/901 (2019.01)
CPC G06F 16/9024 (2019.01) [G06F 15/8046 (2013.01)] 20 Claims
OG exemplary drawing
 
6. An accelerator device, comprising:
a first processing unit comprising at least one of a central processing unit and a vector processing unit, the first processing unit configured to modify a structure of a graph dataset by adding and removing vertices and edges of the graph dataset; and
a second processing unit coupled with the first processing unit and configured to perform computations based on data values in the modified graph dataset.