US 12,248,430 B2
Overlay layer for network of processor cores
Davor Capalija, Toronto (CA); Ivan Matosevic, Toronto (CA); Jasmina Vasiljevic, Toronto (CA); Utku Aydonat, Toronto (CA); Andrew Lewycky, Toronto (CA); S. Alexander Chin, Toronto (CA); Ljubisa Bajic, Toronto (CA); Alex Cejkov, Toronto (CA); and Milos Trajkovic, Toronto (CA)
Assigned to Tenstorrent Inc., Toronto (CA)
Filed by Tenstorrent Inc., Toronto (CA)
Filed on Sep. 14, 2022, as Appl. No. 17/945,045.
Application 17/945,045 is a continuation in part of application No. 16/942,492, filed on Jul. 29, 2020, granted, now 11,467,846.
Claims priority of provisional application 62/882,065, filed on Aug. 2, 2019.
Prior Publication US 2023/0041130 A1, Feb. 9, 2023
Int. Cl. G06F 15/78 (2006.01); G06F 5/01 (2006.01)
CPC G06F 15/7807 (2013.01) [G06F 5/01 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A multicore processor stack, stored on non-transitory computer readable media in a multicore processor, comprising:
a computation layer, for conducting computations using a set of processing cores in the multicore processor, with executable instructions for a set of processing pipelines in the set of processing cores;
a network-on-chip layer, for connecting the set of processing cores in the multicore processor, with executable instructions for a set of routers and a set of network interface units in the multicore processor;
a set of programmable controllers, with executable instructions for reformatting computational data from the computation layer for transmission through the network-on-chip layer, wherein each processing core in the set of processing cores has a programmable controller from the set of programmable controllers; and
a NoC overlay layer that logically isolates the computation layer and the network-on-chip layer.