US 12,248,422 B2
Systems and methods for lane management in a communication bus
Tomer Rafael Ben-Chen, Amikam (IL); Yaron Shachar, Raanana (IL); and David Teb, Haifa (IL)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on May 9, 2023, as Appl. No. 18/314,359.
Prior Publication US 2024/0378164 A1, Nov. 14, 2024
Int. Cl. G06F 13/40 (2006.01); G06F 1/10 (2006.01)
CPC G06F 13/4068 (2013.01) [G06F 1/10 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A baseband processor (BBP) comprising:
a bus interface configured to couple to a communication bus, the bus interface comprising:
one or more uplink lanes; and
one or more downlink lanes; and
a control circuit coupled to the bus interface and configured to:
adjust a bandwidth for the communication bus by changing a duty cycle associated with the communication bus; and
while the communication bus is active:
cycle the one or more downlink lanes on and off during a receive slot; and
turn on at least one of the one or more uplink lanes on during an entirety of a transmit slot.