US 12,248,418 B2
Efficient signaling scheme for high-speed ultra short reach interfaces
Ramin Farjadrad, Los Altos, CA (US); and Paul Langner, Fremont, CA (US)
Assigned to MARVELL ASIA PTE LTD, Singapore (SG)
Filed by MARVELL ASIA PTE LTD, Singapore (SG)
Filed on Nov. 17, 2023, as Appl. No. 18/512,744.
Application 18/512,744 is a continuation of application No. 17/893,886, filed on Aug. 23, 2022, granted, now 11,822,369.
Application 17/893,886 is a continuation of application No. 17/108,519, filed on Dec. 1, 2020, granted, now 11,422,961, issued on Aug. 23, 2022.
Application 17/108,519 is a continuation of application No. 15/451,920, filed on Mar. 7, 2017, granted, now 10,855,498, issued on Dec. 1, 2020.
Claims priority of provisional application 62/341,871, filed on May 26, 2016.
Claims priority of provisional application 62/314,237, filed on Mar. 28, 2016.
Prior Publication US 2024/0086350 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/36 (2006.01); H04L 7/00 (2006.01); H04L 25/20 (2006.01)
CPC G06F 13/36 (2013.01) [H04L 7/0091 (2013.01); H04L 25/20 (2013.01)] 15 Claims
OG exemplary drawing
 
6. A semiconductor device package, comprising:
a first group of IC chips disposed in the semiconductor device package and including a first integrated circuit (IC) chip to transmit first data off the first IC chip; and
a transfer IC chip disposed in the semiconductor device package, the transfer IC chip to receive the first data from the first IC chip via at least one first bidirectional link, the transfer IC chip including switching circuitry to selectively forward the first data to one of a first output interface or a second output interface, the first output interface communicatively coupled to a third IC chip of a second group of IC chips via at least one second bidirectional link, the second group of IC chips being disposed in the semiconductor device package, the second output interface configured to output the first data from the semiconductor device package;
wherein the at least one first bidirectional link further comprises a first set of ultra-short reach (USR) bidirectional signaling links connecting the first group of IC chips to the transfer IC chip;
wherein the at least one second bidirectional link further comprises a second set of USR bidirectional signaling links connecting the second group of IC chips to the transfer IC chip; and
wherein each of the USR bidirectional signaling links comprises a trace length of less than one inch.