US 12,248,416 B2
Programmable user-defined peripheral-bus device implementation using data-plane accelerator (DPA)
Daniel Marcovitch, Yokneam Illit (IL); Eliav Bar-Ilan, Or Akiva (IL); Ran Avraham Koren, Beijing (CN); Liran Liss, Atzmon-Segev (IL); Oren Duer, Kochav Yair (IL); and Shahaf Shuler, Kibbutz Lochamei Hagetaot (IL)
Assigned to Mellanox Technologies, Ltd, Yokneam (IL)
Filed by MELLANOX TECHNOLOGIES, LTD., Yokneam (IL)
Filed on May 6, 2024, as Appl. No. 18/655,386.
Application 18/655,386 is a continuation of application No. 17/979,013, filed on Nov. 2, 2022, granted, now 12,007,921.
Prior Publication US 2024/0289288 A1, Aug. 29, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/28 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/28 (2013.01) [G06F 13/4221 (2013.01); G06F 2213/0024 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A network adapter, comprising:
a network interface, to communicate with a network;
a bus interface, to communicate with an external device over a peripheral bus;
a hardware-implemented data-path, comprising a plurality of packet-processing engines to process data units exchanged between the network and the external device, the packet-processing engines including an address-translation engine to translate between virtual addresses in a first address space and addresses assigned to the data units in a second address space; and
a programmable Data-Plane Accelerator (DPA), to expose on the peripheral bus a User-Defined Peripheral-bus Device (UDPD), to run user-programmable logic that implements the UDPD, and to process transactions issued from the external device to the UDPD by reusing one or more of the packet-processing engines of the data-path, including re-using the address-translation engine to translate between virtual addresses in a third address space and addresses assigned to UDPD data units associated with the UDPD in a fourth address space.