| CPC G06F 13/24 (2013.01) [G06F 13/4221 (2013.01); G06F 2213/0026 (2013.01)] | 4 Claims |

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1. A data transmission control device, disposed in a chip that comprises a Peripheral Component Interconnect Express (PCIe) interface and coupled to a memory that comprises a block, the data transmission control device comprising:
a control circuit;
a PCIe interface controller configured to receive a data; and
an address monitoring circuit configured to issue an interrupt to the control circuit in response to the data being written into the block;
wherein the address monitoring circuit issues the interrupt when the chip operates in an Endpoint (EP) mode;
wherein the block is located at a predetermined address of the memory, and the data has a target address, the address monitoring circuit comprising:
a comparison circuit configured to determine whether the predetermined address is identical to the target address; and
an interrupt controller coupled to the comparison circuit and configured to generate the interrupt when the predetermined address is identical to the target address.
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