US 12,248,413 B1
Universal memory interface utilizing die-to-die (D2D) interfaces between chiplets
Ramin Farjadrad, Los Altos, CA (US); Syrus Ziai, Los Altos, CA (US); and Curtis McAllister, Los Altos, CA (US)
Assigned to Eliyan Corporation, Santa Clara, CA (US)
Filed by Eliyan Corporation, Santa Clara, CA (US)
Filed on May 1, 2024, as Appl. No. 18/652,675.
Claims priority of provisional application 63/543,517, filed on Oct. 11, 2023.
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/16 (2006.01)
CPC G06F 13/1668 (2013.01) [G06F 13/1689 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A chiplet-based multi-chip module (MCM), comprising:
a package substrate;
a host integrated circuit (IC) chiplet coupled to the package substrate and comprising:
at least one processing element;
a communications fabric switchably coupled to the at least one processing element; and
a primary die-to-die (D2D) interface to transfer memory information via a packet protocol from the at least one processing element via the communications fabric;
at least one memory chiplet comprising:
a secondary D2D interface coupled to the primary D2D interface via multiple signaling lanes;
a memory port comprising a memory physical interface of at least one first memory type for accessing memory storage of the at least one first memory type; and
wherein the multiple signaling lanes are configured to route information packets controlled by the communications fabric between the host IC chiplet and the at least one memory chiplet.