US 12,248,411 B2
Data burst queue management
Eric N. Lee, San Jose, CA (US); Luigi Pilolli, L'Aquila (IT); Ali Feiz Zarrin Ghalam, Sunnyvale, CA (US); Xiangyu Tang, San Jose, CA (US); and Daniel Jerre Hubbard, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on May 9, 2023, as Appl. No. 18/144,957.
Claims priority of provisional application 63/340,762, filed on May 11, 2022.
Prior Publication US 2023/0367723 A1, Nov. 16, 2023
Int. Cl. G06F 13/16 (2006.01); G06F 12/0879 (2016.01); G06F 13/32 (2006.01)
CPC G06F 13/1626 (2013.01) [G06F 12/0879 (2013.01); G06F 13/32 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a set of memory dies; and
a processing device, operatively coupled with the set of memory dies, to perform operations comprising:
establishing a queue storing a list of data burst commands to be communicated via a multiplexed interface coupled to the set of memory dies;
communicating, during a first time period, a first data burst command in the queue to a first memory die of the set of memory dies via the multiplexed interface; and
communicating, during a second time period, a second data burst command in the queue to a second memory die of the set of memory dies via the multiplexed interface, wherein a first latency associated with execution of the first data burst command occurs during the communicating of the second data burst command during the second time period.