US 12,248,405 B2
Address boundary functions for physical and localized addresses
Dean Liberty, Nashua, NH (US); Robert P. Adler, Santa Clara, CA (US); Henry Cook, Berkeley, CA (US); Abderrahmane Sensaoui, Marseilles (FR); and Perrine Peresse, Tourrettes-sur-Loup (FR)
Assigned to SiFive, Inc., Santa Clara, CA (US)
Filed by SiFive, Inc., San Mateo, CA (US)
Filed on Sep. 26, 2023, as Appl. No. 18/474,411.
Claims priority of provisional application 63/442,600, filed on Feb. 1, 2023.
Prior Publication US 2024/0256462 A1, Aug. 1, 2024
Int. Cl. G06F 12/10 (2016.01)
CPC G06F 12/10 (2013.01) 20 Claims
OG exemplary drawing
 
1. An integrated circuit for executing instructions comprising:
a processor configured to transmit a memory request to a target module over a bus of the integrated circuit, wherein the memory request requests access to one or more memory mapped resources, wherein the memory request includes a physical address;
a first boundary function configured to translate the physical address to a relative address, wherein the relative address operates in or applies to a different address space than an address space that the physical address operates in or applies to, wherein the first boundary function is programmed to identify the physical address, subtract a physical base address from the physical address, and add a relative base address to a subtracted physical address to generate the relative address;
a second boundary function configured to translate the relative address to the physical address, wherein the second boundary function is programmed to identify the relative address, subtract the base relative address, and add the physical base address to a subtracted relative address to generate the physical address; and
a device configured to utilize the physical address transmitted by the second boundary function.