US 12,248,402 B2
Bandwidth boosted stacked memory
Krishna T. Malladi, San Jose, CA (US); Mu-Tien Chang, Santa Clara, CA (US); Dimin Niu, Sunnyvale, CA (US); and Hongzhong Zheng, Los Gatos, CA (US)
Assigned to Samsung Electronics Co., Ltd., Yongin-si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Nov. 28, 2022, as Appl. No. 18/070,328.
Application 17/156,362 is a division of application No. 16/439,613, filed on Jun. 12, 2019, granted, now 10,915,451, issued on Feb. 9, 2021.
Application 18/070,328 is a continuation of application No. 17/156,362, filed on Jan. 22, 2021, granted, now 11,513,965, issued on Nov. 29, 2022.
Claims priority of provisional application 62/846,406, filed on May 10, 2019.
Prior Publication US 2023/0087747 A1, Mar. 23, 2023
Int. Cl. G06F 12/0879 (2016.01); G11C 11/417 (2006.01)
CPC G06F 12/0879 (2013.01) [G11C 11/417 (2013.01); G06F 2212/603 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for memory addressing, the method comprising:
determining, by a system comprising a memory device coupled to a host processor via a first channel and a second channel, a first spatial proximity of sequential memory accesses with a first function,
the first channel comprising:
a first portion having a first width less than a full width of the first channel; and
a second portion having a second width less than the full width of the first channel, and
the second channel comprising a third portion having a third width that is different from the first width or the second width,
wherein a full width of the first channel and a full width of the second channel are operational.