| CPC G06F 12/0811 (2013.01) [G06F 12/0246 (2013.01); G06F 12/0846 (2013.01); G06F 12/0891 (2013.01); G06F 13/1605 (2013.01); G06F 13/1668 (2013.01)] | 20 Claims |
|
1. An apparatus, comprising:
cache circuitry that includes multiple cache entry circuits, wherein a given cache entry circuit is configured to store a cache block;
tag circuitry configured to maintain a tag value shared by multiple cache entry circuits, wherein the tag value is a portion of an address, wherein the portion is shared by cached entries and is maintained for comparison with incoming cache requests to determine hits and misses in the cache circuitry;
cache control circuitry configured to, in response to a miss for a request for a first cache block, initiate a fetch request to a next level cache or memory;
aggregation circuitry configured to:
store, for the tag value, valid fetch information that indicates that:
a first cache entry circuit that shares the tag value has initiated a valid fetch request that has not completed; and
a second cache entry circuit that shares the tag value has initiated a valid fetch request that has not completed; and
aggregate, based on the valid fetch information, fetch requests for the first and second cache entry circuits in response to a determination that requested cache blocks share the tag value, wherein the fetch requests are based on misses in the cache circuitry; and
fetch circuitry configured to initiate a single multi-block fetch operation to the next level cache or memory that returns cache blocks for the aggregated fetch requests.
|