US 12,248,395 B2
Data storage device and method for predictable low-latency in a time-sensitive environment
Devika Nair, Bangalore (IN); and Amit Sharma, Bangalore (IN)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jul. 26, 2023, as Appl. No. 18/226,385.
Claims priority of provisional application 63/471,411, filed on Jun. 6, 2023.
Prior Publication US 2024/0411678 A1, Dec. 12, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 11/08 (2006.01); G06F 12/02 (2006.01)
CPC G06F 12/0215 (2013.01) [G06F 11/08 (2013.01); G06F 2212/1024 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A data storage device comprising:
a non-volatile memory array;
a data cache; and
a processor configured to communicate with the memory and further configured to:
receive, from a host, an indication of a logical block address range that the host will later read;
in response to receiving the indication:
read original data from the non-volatile memory array, wherein the original data is stored in the non-volatile memory array with a set of parity bits; and
store a copy of the data in the non-volatile memory array with fewer, if any, parity bits than what is stored with the original data in the non-volatile memory array;
receive a command from the host to read the logical block; and
in response to receiving the command from the host to read the logical block address range, read, from the non-volatile memory array, the copy of the data instead of the original data, wherein because the copy of the data is stored in the non-volatile memory array with fewer, if any, parity bits than what is stored in the non-volatile memory array with the original data, reading the copy of the data from the non-volatile memory array instead of reading the original data from the non-volatile memory array reduces read latency because fewer parity bits are read from the non-volatile memory array.