CPC G06F 11/1064 (2013.01) [G06F 11/076 (2013.01); G06F 11/0772 (2013.01); G06F 11/106 (2013.01)] | 16 Claims |
1. An apparatus, comprising:
memory circuitry that includes:
memory cells configured to store data;
interface circuitry that includes a first interface configured to transmit data and a second interface configured to transmit parity information for the data;
on-die error correcting code (ECC) circuitry configured to:
check read data from the memory cells for errors; and
correct detected correctable errors to generate corrected data;
link ECC circuitry configured to transmit link parity information via the second interface;
wherein the memory circuitry is configured to:
provide read data to a requesting circuit via the first interface, including one or more sets of corrected data from the on-die ECC circuitry; and
provide a decoding status flag (DSF), including to:
set the DSF to a first value in response to no error being detected for a given set of provided read data;
set the DSF to a second value in response to a correctable error that was detected and corrected by the on-die ECC circuitry to provide a given set of read data;
set the DSF to a third value in response to an uncorrectable error detected by the on-die ECC circuitry; and
transmit the DSF via the same second interface as the link parity information.
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