| CPC G06F 11/0793 (2013.01) [G06F 11/0757 (2013.01); G06F 11/0772 (2013.01); G06F 13/4291 (2013.01)] | 30 Claims |
|
1. A receiving circuit, comprising:
a clock generator circuit configured to generate a base clock signal with a base frequency;
a synchronization circuit configured to synchronize edges in the base clock signal with edges in a Manchester-encoded data signal received over a serial bus; and
a controller configured to:
detect that a first pulse received from the serial bus has a duration corresponding to a pulse duration defined for a first type of sequence start condition (SSC) that indicates a first type of transaction during which the Manchester-encoded data signal is received over the serial bus;
configure a first timer to expire after a first timeout period; and
ignore the first pulse when signaling consistent with the first type of SSC has not been received before the first timer expires.
|