| CPC G06F 1/3293 (2013.01) | 16 Claims |
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1. An apparatus comprising:
circuitry coupled with a single socket multi-core processor, the circuitry to:
map a first portion of cores of the single socket multi-core processor to a first virtual non-uniform memory architecture (NUMA) node and map a second portion of the cores to a second virtual NUMA node, wherein the second portion of the cores does not include any cores included in the first portion of cores;
partition a dynamic random access memory (DRAM) device into multiple segments, each segment capable of having self-refresh operations separately deactivated or activated;
map at least one segment from among the multiple segments to a first virtual local memory of the first virtual NUMA node and map remaining segments from among the multiple segments to a second virtual local memory of the second virtual NUMA node;
cause a memory request to allocate memory for a pinned or a locked page of data to be directed to the first virtual NUMA node, the memory request received from an application to be executed by the single socket multi-core processor; and
cause the memory request for the pinned or locked page of data to be directed to the first virtual NUMA node based on an indication in the memory request that a pinned or locked page is to be allocated to the at least one segment mapped to the first virtual local memory or based on the memory request targeting an allocation of memory for use by the first virtual NUMA node to execute at least a portion of a workload for the application.
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