| CPC G06F 1/3287 (2013.01) [G06F 9/4401 (2013.01); G06F 9/4408 (2013.01); G06F 9/4418 (2013.01); G06F 13/24 (2013.01); G11C 7/1072 (2013.01); G11C 11/40615 (2013.01); Y02D 10/00 (2018.01)] | 20 Claims |

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1. A computer system comprising:
an application processor including a read-only memory (ROM) configured to store a first boot loader, a first memory configured to store a second boot loader, and a second memory configured to store a third boot loader; and
a power management integrated circuit (PMIC) configured to supply first power only to the second memory during a power-down mode, and supply second power to both the first and second memories during a wake-up mode, and
wherein the application processor is configured to:
receive an interrupt signal during the power-down mode; and
perform a secure boot operation of the third boot loader based on the interrupt signal.
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