US 12,248,350 B2
Die-to-die dynamic clock and power gating
Dany Davidov, Tirat Carmel (IL); Misbah Ramadan, Haifa (IL); Itamar Rozen, Givat Ela (IL); and Tzach Zemer, Megadim (IL)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Feb. 27, 2023, as Appl. No. 18/174,985.
Application 18/174,985 is a continuation of application No. 17/318,670, filed on May 12, 2021, granted, now 11,592,889.
Prior Publication US 2023/0214350 A1, Jul. 6, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 1/3203 (2019.01); G06F 1/18 (2006.01); G06F 13/36 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 1/3203 (2013.01) [G06F 1/18 (2013.01); G06F 13/36 (2013.01); G06F 13/4022 (2013.01); G06F 13/4291 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising: a plurality of integrated circuits located on respective dies, wherein the plurality of integrated circuits is connected by a network, respective portions of which are located on different ones of the respective dies, and wherein the plurality of integrated circuits and the network are configured to operate as a single logical computing system;
wherein a given integrated circuit of the plurality of integrated circuits includes a processor circuit configured to use a common bus protocol to access a circuit block on another integrated circuit of the plurality of integrated circuits, and to use the common bus protocol to access a circuit block on the given integrated circuit;
wherein the plurality of integrated circuits is configured to enter a reduced power mode;
wherein a particular integrated circuit of the plurality of integrated circuits is configured to:
determine that a particular circuit block in the particular integrated circuit has requested to send a transaction to a different circuit block in a different integrated circuit of the plurality of integrated circuits; wake a network circuit in the particular integrated circuit from the reduced power mode; and use the network circuit to assert a wake signal on a node coupled to the different integrated circuit.