US 12,248,349 B2
Layered series-connected power supply circuit and data processing device for supplying power to computing chips connected in series from bottommost layer to highest layer
Yang Gao, Guangdong (CN); Yuefeng Wu, Guangdong (CN); and Zuoxing Yang, Guangdong (CN)
Assigned to SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 17/922,905
Filed by SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Jul. 13, 2021, PCT No. PCT/CN2021/105918
§ 371(c)(1), (2) Date Nov. 2, 2022,
PCT Pub. No. WO2022/057415, PCT Pub. Date Mar. 24, 2022.
Claims priority of application No. 202010980205.6 (CN), filed on Sep. 17, 2020.
Prior Publication US 2023/0176637 A1, Jun. 8, 2023
Int. Cl. G06F 1/26 (2006.01)
CPC G06F 1/263 (2013.01) 6 Claims
OG exemplary drawing
 
1. A data processing device including a control board and a hash board connected to the control board, wherein the hash board comprises a series-connected power supply circuit, comprising:
at least two layers of to-be-powered chips connected in series between a first power supply end and a second power supply end, with a highest-layer to-be-powered chip in the at least two layers of to-be-powered chips connected to the first power supply end, and a bottommost-layer to-be-powered chip in the at least two layers of to-be-powered chips connected to the second power supply end; and
at least two layers of auxiliary power supply units, wherein each layer of auxiliary power supply units is respectively connected to each layer of the to-be-powered chips;
wherein the first power supply end is configured to receive a reference voltage, and wherein the voltages of the to-be-powered chips and the auxiliary power supply units are set or adjusted by referring to the reference voltage at the first power supply end; and
wherein each layer of the to-be-powered chips has a main working voltage input end, an auxiliary working voltage input end, and a power supply negative terminal, wherein the first power supply end is connected to the main working voltage input end of the highest-layer to-be-powered chip, and the power supply negative terminal of each layer of the to-be-powered chips is connected to the main working voltage input end of a next-layer to-be-powered chip, so that a main working voltage is respectively provided for each layer of the to-be-powered chips via the main working voltage input end;
the power supply negative terminal of each layer of the auxiliary power supply units is connected to the power supply negative terminal of the to-be-powered chip on the same layer, and an output end of each layer of the auxiliary power supply units is connected to the auxiliary working voltage input end of the to-be-powered chip on the same layer, wherein an input end of at least one layer of auxiliary power supply unit is connected to an external power supply end for power supply, and input ends of remaining layers of the auxiliary power supply units are successively connected to main working voltage input ends of to-be-powered chips on corresponding layers under the highest-layer to-be-powered chip, so that an auxiliary working voltage is provided for a connected to-be-powered chip via the auxiliary working voltage input end;
wherein a power supply negative electrode of the control board is connected to a power supply positive electrode of the hash board, or the power supply negative electrode of the control board is connected to a power supply negative terminal of a highest-layer to-be-powered chip in the series-connected power supply circuit;
wherein control signals and communication signals from the control board are accessed to the series-connected power supply circuit via a communication interface of the highest-layer to-be-powered chip in the series-connected power supply circuit and pass through to-be-powered chips connected in series to lower layers for communication.