| CPC G06F 1/08 (2013.01) [G01R 25/00 (2013.01); G06F 1/10 (2013.01); H03D 7/1441 (2013.01)] | 19 Claims |

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1. A phase detector circuitry comprising:
first mixer circuitry configured to receive a first clock signal and a second clock signal, the first mixer circuitry comprising:
a first plurality of transistors comprising:
first transistors comprising a first input transistor and a second input transistor comprising gate nodes configured to receive the first clock signal;
second transistors comprising a third input transistor and a fourth input transistor comprising gate nodes configured to receive the second clock signal; and
a first output transistor configured to output a first output signal, wherein the first output signal corresponds to a first phase difference between the first clock signal and the second clock signal, wherein the third input transistor is coupled between the second input transistor and the first output transistor, and the first input transistor is coupled between the fourth input transistor and the first output transistor.
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