US 12,248,334 B2
Clock circuits, computing chips, hash boards and data processing devices
Nan Li, Guangdong (CN); Zuoxing Yang, Guangdong (CN); Zhijun Fan, Guangdong (CN); Haifeng Guo, Guangdong (CN); and Chao Xu, Guangdong (CN)
Assigned to SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Shenzhen (CN)
Appl. No. 18/008,029
Filed by SHENZHEN MICROBT ELECTRONICS TECHNOLOGY CO., LTD., Guangdong (CN)
PCT Filed Mar. 30, 2021, PCT No. PCT/CN2021/083722
§ 371(c)(1), (2) Date Dec. 2, 2022,
PCT Pub. No. WO2021/244113, PCT Pub. Date Dec. 9, 2021.
Claims priority of application No. 202010501270.6 (CN), filed on Jun. 4, 2020.
Prior Publication US 2023/0236622 A1, Jul. 27, 2023
Int. Cl. G06F 1/08 (2006.01); G06F 1/04 (2006.01); G06F 1/10 (2006.01); G06F 9/38 (2018.01); H03K 3/037 (2006.01)
CPC G06F 1/08 (2013.01) [G06F 1/10 (2013.01); G06F 1/04 (2013.01); G06F 9/3869 (2013.01); H03K 3/037 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A clock circuit, comprising M stages of clock drive circuits that are connected in series, M being an integer that is no less than 2, wherein each of the M stages includes N inverters directly connected in series without any intervening element, the N inverters being arranged between an input port and an output port of each stage of the M stages of the clock drive circuits, N being an odd number that is no less than 3, wherein the output port of each stage of the M stages of clock drive circuits provides a clock signal for a corresponding stage of pipeline circuit in a pipeline structure for executing a data processing task.