US 12,248,333 B2
Processor embedded streaming buffer
Joseph Williams, Holmdel, NJ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2021, as Appl. No. 17/358,218.
Prior Publication US 2022/0413852 A1, Dec. 29, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/355 (2018.01); G06F 9/38 (2018.01); G06F 15/78 (2006.01)
CPC G06F 9/30036 (2013.01) [G06F 9/30109 (2013.01); G06F 9/355 (2013.01); G06F 9/3814 (2013.01); G06F 15/7807 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A vector processing unit, comprising:
a buffer configured to store a set of vector data samples that are retrieved from one or more vector registers; and
vector processing circuitry configured to:
for a first vector processor instruction that is executed during a first one of a plurality of clock cycles, perform a first vector processing operation using a first portion of the stored set of vector data samples,
for a second vector processor instruction that is executed during a second one of the plurality of clock cycles, perform a second vector processing operation using a second portion of the stored set of vector data samples,
wherein a predetermined number of the first portion of the stored set of vector data samples used to perform the first vector processing operation are the same as the second portion of the stored set of vector data samples used to perform the second vector processing operation.