US 12,248,022 B2
Method and apparatus for detecting defective logic devices
Chi-Che Wu, Hsinchu (TW); Tsung-Yang Hung, Hsinchu County (TW); Ming-Yih Wang, Hsin-Chu (TW); and Jia-Ming Guo, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD., Hsinchu (TW)
Filed on Apr. 28, 2023, as Appl. No. 18/308,768.
Application 18/308,768 is a continuation of application No. 16/989,726, filed on Aug. 10, 2020, granted, now 11,675,004.
Claims priority of provisional application 63/024,874, filed on May 14, 2020.
Prior Publication US 2023/0273257 A1, Aug. 31, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G01R 31/3177 (2006.01); G01R 31/30 (2006.01); G01R 31/317 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/3008 (2013.01); G01R 31/31721 (2013.01); G01R 31/31725 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus for testing a device under test (DUT), comprising:
a power supply device configured to provide a first voltage in a first time duration and a second voltage in a second time duration to the DUT;
a clock device configured to provide a clock signal to the DUT in the first time duration and stop providing the clock signal to the DUT in the second time duration; and
a data generating device configured to provide first data to the DUT in the first time duration, wherein
the second voltage is lower than the first voltage;
the DUT comprises a first number of information storage units connected in series;
the first data comprises a second number of bits; and
the second number is identical to the first number.