US 12,248,021 B2
Debug trace microsectors
Sean R. Atsatt, Santa Cruz, CA (US); and Ilya K. Ganusov, San Jose, CA (US)
Assigned to Altera Corporation, San Jose, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2020, as Appl. No. 17/132,683.
Prior Publication US 2022/0196735 A1, Jun. 23, 2022
Int. Cl. G01R 31/3177 (2006.01); G01R 31/317 (2006.01); G06F 15/78 (2006.01); H03K 19/17758 (2020.01)
CPC G01R 31/3177 (2013.01) [G01R 31/31705 (2013.01); G06F 15/7825 (2013.01); H03K 19/17758 (2020.01)] 13 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a first network-on-chip disposed around at least a partial perimeter of a plurality of microsectors arranged in a row and column grid; and
a first microsector of the plurality of microsectors, wherein the first microsector is coupled to a first row controller, the first microsector comprising:
a plurality of logic access blocks, each logic access block coupled to a respective one of a plurality of data registers;
a plurality of routing blocks, each routing block comprising a first highly pipelined (HIPI) register chain and a second HIPI register chain, wherein at least one of the plurality of data registers is coupled to at least one of the first HIPI register chain and second HIPI register chain; and
a control block comprising a first shift register chain configurable to shift data out of the first microsector to the first row controller and a second shift register chain configurable to shift data into the first microsector from the first row controller.