US 12,247,870 B2
Photodetector device having avalanche photodiodes two-dimensionally arranged on a semiconductor layer and quenching element connected in series to the photodiodes
Takuya Fujita, Hamamatsu (JP); Yusei Tamura, Hamamatsu (JP); Kenji Makino, Hamamatsu (JP); Takashi Baba, Hamamatsu (JP); and Koei Yamamoto, Hamamatsu (JP)
Assigned to HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
Filed by HAMAMATSU PHOTONICS K.K., Hamamatsu (JP)
Filed on Jul. 18, 2023, as Appl. No. 18/223,277.
Application 18/223,277 is a continuation of application No. 17/384,915, filed on Jul. 26, 2021, granted, now 11,860,032.
Application 17/384,915 is a continuation of application No. 16/963,312, granted, now 11,125,616, issued on Sep. 21, 2021, previously published as PCT/JP2019/002352, filed on Jan. 24, 2019.
Claims priority of application No. 2018-011824 (JP), filed on Jan. 26, 2018.
Prior Publication US 2023/0358607 A1, Nov. 9, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G01J 1/44 (2006.01); H01L 27/144 (2006.01); H01L 31/02 (2006.01); H01L 31/107 (2006.01)
CPC G01J 1/44 (2013.01) [H01L 27/1446 (2013.01); H01L 31/02027 (2013.01); H01L 31/107 (2013.01); G01J 2001/442 (2013.01); G01J 2001/4466 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A photodetector device comprising:
a first layer in which a plurality of avalanche photodiodes arranged to operate in a Geiger mode are two-dimensionally arranged, the first layer being formed from compound semiconductor; and
a second layer including a plurality of output units, overlapping the first layer, and being formed from silicon,
wherein each of the output units includes a quenching element connected in series to one of the plurality of avalanche photodiodes,
the quenching element includes a passive quenching element,
the second layer includes a capacitative element connected in series to one of the avalanche photodiodes and connected in parallel to the passive quenching element, and
the passive quenching element is formed by a first polysilicon/metal layer provided in the second layer, the capacitative element is formed by a second polysilicon/metal layer provided in the second layer, a dielectric layer stacked on the second polysilicon/metal layer, and a third polysilicon/metal layer stacked on the dielectric layer, and the first polysilicon/metal layer is formed at the same height as in the second polysilicon/metal layer or the third polysilicon/metal layer in a thickness direction of the second layer.