US 11,925,031 B2
Arrays of capacitors and arrays of memory cells
Fatma Arzum Simsek-Ege, Boise, ID (US); and Durai Vishak Nirmal Ramaswamy, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 22, 2022, as Appl. No. 17/950,968.
Application 17/950,968 is a division of application No. 16/941,174, filed on Jul. 28, 2020, granted, now 11,476,262.
Prior Publication US 2023/0013333 A1, Jan. 19, 2023
Int. Cl. H10B 53/30 (2023.01); H01L 21/768 (2006.01); H01L 49/02 (2006.01); H10B 12/00 (2023.01); H10B 53/10 (2023.01)
CPC H10B 53/30 (2023.02) [H01L 21/7688 (2013.01); H01L 28/60 (2013.01); H10B 12/0335 (2023.02); H10B 53/10 (2023.02)] 16 Claims
OG exemplary drawing
 
1. An array of capacitors comprising:
a plurality of horizontally-spaced groups individually comprising a plurality of horizontally-spaced lower capacitor electrodes;
a capacitor insulator over the lower capacitor electrodes;
an upper capacitor electrode that is common to all capacitors in an individual group comprised by the plurality of horizontally-spaced groups; the capacitors in the individual group comprising one of the lower capacitor electrodes, the capacitor insulator, and the common upper capacitor electrode;
a horizontally-elongated conductive line atop and directly electrically coupled with the upper capacitor electrode in the individual group; and
horizontally-spaced pillars between immediately-adjacent individual groups comprised by the plurality of horizontally-spaced individual groups, the pillars being of a same size and shape relative to the lower capacitor electrodes and being circuit inoperative.