US 11,925,028 B2
Semiconductor memory device and manufacturing method thereof
Jae Taek Kim, Icheon-si (KR); and Hye Yeong Jung, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Jul. 21, 2020, as Appl. No. 16/934,641.
Claims priority of application No. 10-2020-0011206 (KR), filed on Jan. 30, 2020.
Prior Publication US 2021/0242231 A1, Aug. 5, 2021
Int. Cl. H01L 21/00 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/10 (2023.01); H10B 41/40 (2023.01); H10B 41/50 (2023.01); H10B 43/10 (2023.01); H10B 43/50 (2023.01); H10B 63/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 43/50 (2023.02) [H01L 23/5226 (2013.01); H01L 23/528 (2013.01); H10B 41/10 (2023.02); H10B 41/40 (2023.02); H10B 41/50 (2023.02); H10B 43/10 (2023.02); H10B 63/30 (2023.02); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 16 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a peripheral transistor;
a first insulating layer covering the peripheral transistor;
a source layer on the first insulating layer;
a stack structure including conductive patterns on the source layer;
a peripheral contact structure penetrating the stack structure and the source layer, the peripheral contact structure being electrically connected to the peripheral transistor; and
a word line contact electrically connected to at least one of the conductive patterns,
wherein the stack structure includes a stepped structure including a step side surface and a step top surface,
wherein the peripheral contact structure is in contact with the step side surface, and
wherein the peripheral contact structure is electrically connected to the word line contact.