CPC H10B 43/30 (2023.02) [H01L 21/823462 (2013.01); H01L 21/823857 (2013.01); H10B 10/18 (2023.02); H10B 12/50 (2023.02); H10B 20/367 (2023.02); H10B 41/40 (2023.02); H10B 43/40 (2023.02)] | 8 Claims |
1. A semiconductor device comprising a memory cell and a switch circuit formed on a semiconductor substrate,
wherein the switch circuit is disposed outside the memory cell and electrically connected to the memory cell,
wherein the memory cell includes a plurality of transistors including a first transistor,
wherein the switch circuit comprises a second transistor electrically connected to the first transistor,
wherein the second transistor includes:
a first word gate formed on a first gate insulating film;
a second word gate formed on a second gate insulating film having a thickness thicker than the first gate insulating film,
wherein in the second transistor, when a current flows through the switch circuit, a first voltage is supplied from the outside of the switch circuit, so that a first region of the semiconductor substrate under the first word gate becomes conductive state,
wherein in the second transistor, when a current flows through the switch circuit, a second voltage is supplied from the outside of the switch circuit, so that a second region of the semiconductor substrate under the first coupling gate becomes conductive state, and
wherein the second voltage is higher than the first voltage.
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