CPC H04N 23/60 (2023.01) [G06F 9/4812 (2013.01); G06F 9/4881 (2013.01)] | 20 Claims |
1. An image signal processor comprising:
a command queue circuit configured to store a plurality of commands and sequentially provide the plurality of commands one by one, each command of the plurality of commands including an interrupt control value corresponding to each image unit of a plurality of image units, the plurality of commands being received from a control processor;
an image processing engine configured to receive the plurality of image units and sequentially process the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit; and
an interrupt control circuit configured to receive the interrupt control value from the command queue circuit, determine one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generate an interrupt signal based on the output interrupt event signals.
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