CPC H04N 19/91 (2014.11) [H04N 19/127 (2014.11); H04N 19/156 (2014.11); H04N 19/174 (2014.11); H04N 19/436 (2014.11)] | 20 Claims |
1. A video encoding pipeline circuitry comprising:
a first transcode engine configured to:
encode a first portion of a bin stream to determine a first bit stream comprising first encoded image data that indicates a first coding group row in an image frame; and
determine neighbor data;
a data buffer communicatively coupled to the first transcode engine and configured to receive the neighbor data from the first transcode engine; and
a second transcode engine communicatively coupled to the data buffer and configured to:
receive the neighbor data from the data buffer; and
while the first transcode engine encodes the first portion of the bin stream, encode a second portion of the bin stream, based on the neighbor data, to determine a second bit stream comprising second encoded image data that indicates a second coding group row in the image frame.
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