US 11,924,456 B2
Image encoder and related non-transitory computer readable medium for image decoding
Kiyofumi Abe, Osaka (JP); Takahiro Nishi, Nara (JP); Tadamasa Toma, Osaka (JP); Ryuichi Kanoh, Osaka (JP); Chong Soon Lim, Singapore (SG); Ru Ling Liao, Singapore (SG); Hai Wei Sun, Singapore (SG); Sughosh Pavan Shashidhar, Singapore (SG); Han Boon Teo, Singapore (SG); and Jing Ya Li, Singapore (SG)
Assigned to PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA, Torrance, CA (US)
Filed by Panasonic Intellectual Property Corporation of America, Torrance, CA (US)
Filed on Dec. 15, 2022, as Appl. No. 18/066,873.
Application 18/066,873 is a continuation of application No. 18/065,977, filed on Dec. 14, 2022.
Application 18/065,977 is a continuation of application No. 18/065,513, filed on Dec. 13, 2022.
Application 18/065,513 is a continuation of application No. 18/064,774, filed on Dec. 12, 2022.
Application 18/064,774 is a continuation of application No. 17/506,443, filed on Oct. 20, 2021, granted, now 11,563,969.
Application 17/506,443 is a continuation of application No. 16/572,323, filed on Sep. 16, 2019, granted, now 11,223,844, issued on Jan. 11, 2022.
Application 16/572,323 is a continuation of application No. PCT/JP2018/030059, filed on Aug. 10, 2018.
Claims priority of provisional application 62/698,785, filed on Jul. 16, 2018.
Claims priority of provisional application 62/548,631, filed on Aug. 22, 2017.
Prior Publication US 2023/0118198 A1, Apr. 20, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 19/51 (2014.01); H04N 19/176 (2014.01); H04N 19/182 (2014.01)
CPC H04N 19/51 (2014.11) [H04N 19/176 (2014.11); H04N 19/182 (2014.11)] 3 Claims
OG exemplary drawing
 
1. An encoder comprising:
circuitry; and
a memory coupled to the circuitry;
wherein the circuitry, in operation, performs a partition process including:
obtaining a current block from a coding tree unit (CTU);
selecting, from a first set of motion vector candidates, a first motion vector for a first partition in the current block;
calculating first values of a set of pixels between the first partition and a second partition in the current block, using the first motion vector for the first partition;
selecting, from a second set of motion vector candidates, a second motion vector for the second partition;
calculating second values of the set of pixels, using the second motion vector for the second partition; and
calculating third values of the set of pixels by weighting the first values and the second values, and
when a ratio of a width to a height of the current block is larger than 4 or a ratio of the height to the width of the current block is larger than 4, the circuitry disables the partition process.