| CPC H04N 19/119 (2014.11) [H04N 19/137 (2014.11); H04N 19/176 (2014.11); H04N 19/52 (2014.11)] | 3 Claims |
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1. An encoder, comprising:
circuitry; and
memory, wherein
using the memory, the circuitry:
obtains an image block from a coding tree unit (CTU);
determines to perform first inter prediction or second inter prediction based on information on inter prediction, the first inter prediction including a bi-directional optical flow (BIO) process, the second inter prediction including a motion compensation process, the second inter prediction not including the BIO process; and
encodes the image block based on the determined inter prediction process, wherein,
when the BIO process is determined to be performed, the circuitry (i) obtains first prediction images for the image block, (ii) obtains gradient images for the first prediction images by determining difference values between adjacent pixels, and (iii) generates a prediction image for the image block using the first prediction images and the gradient images, and
when the motion compensation process is determined to be performed, the circuitry (i) determines a plurality of partitions in the image block, (ii) obtains a second prediction image for each of the plurality of partitions, and (iii) generates a prediction image for the image block using the second prediction images, wherein,
the information includes a flag.
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