US 11,923,977 B1
Decoder success predictor signaling for adjusting MIRS scheduling policy
Amit Bar-Or Tillinger, Tel-Aviv (IL); Gideon Shlomo Kutz, Ramat Hasharon (IL); Assaf Touboul, Netanya (IL); and Tal Oved, Modiin (IL)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 26, 2022, as Appl. No. 17/822,560.
Int. Cl. H04L 1/00 (2006.01); H03M 13/00 (2006.01); H03M 13/11 (2006.01)
CPC H04L 1/005 (2013.01) [H03M 13/1105 (2013.01); H03M 13/611 (2013.01)] 16 Claims
OG exemplary drawing
 
1. An apparatus for wireless communication at a user equipment (UE) comprising:
at least one memory; and
at least one processor coupled to the at least one memory and, based at least in part on information stored in the at least one memory, the at least one processor is configured to:
transmit, to a network node, an indication that the UE skips decoding of code blocks based on a decoder success prediction capability; and
receive, from the network node in response to the indication, a transmission including one or more code blocks based on the indication that the UE skips decoding of code blocks based on the decoder success prediction capability, wherein, for each code block of the one or more code blocks, the at least one processor is further configured to:
calculate a decoding likelihood of the code block based on at least one of an input log likelihood ratio (LLR) of the transmission or a first low density parity check (LDPC) iteration of the transmission; and
decode the code block of the transmission in response to the calculated decoding likelihood of the code block being greater than a threshold; or
skip decoding of the code block in response to the calculated decoding likelihood of the code block being less than the threshold.