US 11,923,910 B1
CMOS circuit
Christian Rasmussen, Kongens Lyngby (DK); Ian Dedic, London (GB); and Benny Mikkelsen, Newton, MA (US)
Assigned to Acacia Communications, Inc., Maynard, MA (US)
Filed by Acacia Communications, Inc., Maynard, MA (US)
Filed on Nov. 20, 2021, as Appl. No. 17/531,733.
Claims priority of provisional application 63/116,498, filed on Nov. 20, 2020.
Int. Cl. H04B 10/00 (2013.01); H04B 1/04 (2006.01); H04B 10/556 (2013.01); H04B 10/80 (2013.01); H04J 14/00 (2006.01)
CPC H04B 10/803 (2013.01) [H04B 1/04 (2013.01); H04B 10/556 (2013.01); H04B 2001/0408 (2013.01)] 21 Claims
OG exemplary drawing
 
1. A CMOS integrated circuit comprising:
digital-to-analogue converters (DACs);
analogue-to-digital converters (ADCs);
a digital signal processor (DSP);
on-chip switching;
an on-chip processor; and
logic enabling the CMOS integrated circuit to:
receive data from a plurality of data sources in a 5G network;
combine the data from the plurality of data sources into a single data stream;
encode the single data stream using the DSP; and
cause the encoded single data stream to be transmitted to another device in the 5G network,
wherein the transmission is over a transmission medium, and
wherein the transmission medium is chosen from the group consisting of an optical link, a mm Wave link, a radio link, and a SERDES link.