US 11,923,869 B2
Data storage device with dynamic mapping of low-density parity check (LDPC) engines
Dattatreya B Nayak, Udupi (IN); Karthik N E, Chickamagalore (IN); Noor Mohamed A A, Kumbakonam (IN); and Yunas Rashid, Srinagar (IN)
Assigned to Western Digital Technologies, Inc., San Jose, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Jun. 14, 2022, as Appl. No. 17/839,626.
Prior Publication US 2023/0403030 A1, Dec. 14, 2023
Int. Cl. G11C 29/00 (2006.01); G06F 3/06 (2006.01); H03M 13/11 (2006.01)
CPC H03M 13/1177 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0631 (2013.01); G06F 3/0656 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); H03M 13/1134 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A data storage device comprising:
a memory including
a plurality of memory dies, and
support circuitry configured to support memory operations at the plurality of memory dies, the support circuitry including a plurality of low-density parity check (LDPC) engines and a plurality of flash controllers (FCs), each of the plurality of FCs corresponding to one of the plurality of memory dies; and
a data storage controller including an interface and a flash translation layer (FTL), the data storage controller is configured to control the interface to output the memory operations to the memory using the FTL and a bus,
wherein the support circuitry is configured to dynamically map the plurality of LDPC engines to the plurality of FCs.