US 11,923,862 B2
Transmission apparatus and transmission system
Fumikazu Inuzuka, Musashino (JP); Kei Kitamura, Musashino (JP); Akira Hirano, Musashino (JP); Masahito Tomizawa, Musashino (JP); and Takuya Ohara, Musashino (JP)
Assigned to NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Tokyo (JP)
Appl. No. 17/311,646
Filed by NIPPON TELEGRAPH AND TELEPHONE CORPORATION, Tokyo (JP)
PCT Filed Dec. 4, 2019, PCT No. PCT/JP2019/047326
§ 371(c)(1), (2) Date Jun. 7, 2021,
PCT Pub. No. WO2020/121903, PCT Pub. Date Jun. 18, 2020.
Claims priority of application No. 2018-231937 (JP), filed on Dec. 11, 2018.
Prior Publication US 2022/0109449 A1, Apr. 7, 2022
Int. Cl. H04B 1/06 (2006.01); H03L 7/18 (2006.01); H04B 1/04 (2006.01); H04J 3/06 (2006.01); H04J 3/14 (2006.01); H04L 7/00 (2006.01)
CPC H03L 7/18 (2013.01) [H04B 1/04 (2013.01); H04B 1/06 (2013.01); H04J 3/062 (2013.01); H04J 3/14 (2013.01); H04L 7/0037 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A transmission apparatus for switching to output any one of a first signal received from another transmission apparatus via a first transmission line and a second signal received from the other transmission apparatus via a second transmission line, the transmission apparatus comprising:
a first reception processor configured to receive the first signal transmitted on the first transmission line and perform a reception process on the first signal;
a second reception processor configured to receive the second signal transmitted on the second transmission line and perform a reception process on the second signal;
an output speed controller configured to control a speed at which the first signal on which the first reception processor has performed the reception process is output and a speed at which the second signal on which the second reception processor has performed the reception process is output;
a system switch configured to select and output any one of the first signal output by the first reception processor and the second signal output by the second reception processor;
an output processor configured to perform an output process for outputting the first signal or the second signal output by the system switch to another device;
a reception side clock generator configured to output a clock signal giving a processing timing to each of the first reception processor, the second reception processor, and the output processor;
a clock frequency controller configured to adjust a frequency of the clock signal giving the processing timing to the output processor; and
a frequency adjustment range calculator configured to calculate an adjustment range of the frequency at the clock frequency controller based on frequency deviation accuracy of the reception side clock generator, frequency deviation accuracy of a transmission side clock generator that outputs a clock signal giving a processing timing to a process of transmitting the first signal and a process of transmitting the second signal at the other transmission apparatus, and a prescribed value of a frequency deviation,
wherein the frequency adjustment range calculator is configured to
acquire the frequency deviation accuracy of the reception side clock generator measured at the transmission apparatus and the frequency deviation accuracy of the transmission side clock generator measured at the other transmission apparatus,
calculate a maximum value of a positive direction of the adjustment range by decreasing a maximum value of the acquired frequency deviation from a minimum value of a positive direction of the prescribed value of the frequency deviation, and
calculate a maximum value of a negative direction of the adjustment range by decreasing a minimum value of the acquired frequency deviation from a minimum value of a negative direction of the prescribed value of the frequency deviation, and
wherein each of the first reception processor, the second reception processor, the output speed controller, the system switch, the output processor, the reception side clock generator, the clock frequency controller, the frequency adjustment range calculator is implemented by:
i) computer executable instructions executed by at least one processor,
ii) at least one circuitry or
iii) a combination of computer executable instructions executed by at least one processor and at least one circuitry.