US 11,923,860 B2
PLL circuit
Masanobu Tsuji, Kyoto (JP)
Assigned to ROHM CO., LTD., Kyoto (JP)
Filed by ROHM CO., LTD., Kyoto (JP)
Filed on Jun. 3, 2022, as Appl. No. 17/831,788.
Application 17/831,788 is a continuation of application No. PCT/JP2020/044205, filed on Nov. 27, 2020.
Claims priority of application No. 2019-220372 (JP), filed on Dec. 5, 2019.
Prior Publication US 2022/0302919 A1, Sep. 22, 2022
Int. Cl. H03L 7/099 (2006.01); H03L 7/081 (2006.01)
CPC H03L 7/0995 (2013.01) [H03L 7/081 (2013.01); H03L 7/0992 (2013.01); H03L 2207/50 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A PLL circuit structured as a Phase Locked Loop (PLL) circuit, comprising:
a digitally controlled oscillator structured such that, during a period in which a selection signal is asserted, a ring oscillator is formed so as to oscillate at a frequency that is changed based on a control code, and such that, during a period in which the selection signal is negated, an injection edge based on a reference clock can be injected; and
a controller structured to control the digitally controlled oscillator,
wherein (A) in a startup period of the PLL circuit, the controller is set to a first mode, and repeats a cycle comprising (i) a process in which the selection signal is asserted so as to oscillate the digitally controlled oscillator, and phase comparison is made between an oscillator clock generated by the digitally controlled oscillator and the reference clock, and (ii) a process in which the selection signal is negated so as to stop the digitally controlled oscillator, and the control code is updated by a binary search based on a result of the phase comparison.