US 11,923,853 B2
Circuit structures to measure flip-flop timing characteristics
Tezaswi Raja, San Jose, CA (US); and Prashant Singh, Santa Clara, CA (US)
Assigned to NVIDIA CORP., Santa Clara, CA (US)
Filed by NVIDIA Corp., Santa Clara, CA (US)
Filed on Feb. 25, 2022, as Appl. No. 17/680,763.
Prior Publication US 2023/0275572 A1, Aug. 31, 2023
Int. Cl. H03K 3/037 (2006.01); H03K 3/03 (2006.01); H03K 5/01 (2006.01); H03K 5/00 (2006.01)
CPC H03K 3/037 (2013.01) [H03K 3/0315 (2013.01); H03K 5/01 (2013.01); H03K 2005/00078 (2013.01)] 16 Claims
OG exemplary drawing
 
1. A ring oscillator comprising:
a plurality of flip-flops configured into a ring;
logic to selectively invert the output of a first flip-flop in the ring and inject the inverted output as a clock signal to a second flip-flop in the ring; and
logic to select (a) a clock-to-Q propagation path for the ring oscillator, (b) a Q path calibration path for the ring oscillator, and (c) a nQ (complement of Q) path calibration for the ring oscillator.