US 11,923,848 B1
Majority or minority logic gate with non-linear input capacitors without reset
Amrita Mathuriya, Portland, OR (US); Rafael Rios, Austin, TX (US); Ikenna Odinaka, Durham, NC (US); Darshak Doshi, Sunnyvale, CA (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Sasikanth Manipatruni, Portland, OR (US)
Assigned to KEPLER COMPUTING INC., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Apr. 20, 2022, as Appl. No. 17/659,994.
Application 17/659,994 is a continuation of application No. 17/659,981, filed on Apr. 20, 2022.
Int. Cl. H03K 19/23 (2006.01); H03K 19/0185 (2006.01); H03K 19/185 (2006.01)
CPC H03K 19/23 (2013.01) [H03K 19/018521 (2013.01); H03K 19/185 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first capacitor to receive a first input, the first capacitor coupled to a node;
a second capacitor to receive a second input, the second capacitor coupled to the node; and
a third capacitor to receive a third input, wherein the third capacitor is coupled to the node, wherein the first capacitor, the second capacitor, and the third capacitor comprise non-linear polar material, and wherein the first capacitor, the second capacitor, and the third capacitor have substantially equal leakages.