US 11,923,845 B1
Timing controlled level shifter circuit
Frank M. Kronmüller, Kirchheim unter Teck (DE); Mahir Uka, Kirchheim unter Teck (DE); and Amedeo Bertone, Ulm (DE)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Sep. 9, 2022, as Appl. No. 17/931,055.
Int. Cl. H03K 19/0185 (2006.01); H03K 3/037 (2006.01)
CPC H03K 19/018521 (2013.01) [H03K 3/037 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
an input circuit configured to:
receive an input signal generated using a first power supply voltage level; and
generate, using the first power supply voltage level, a first control signal and a second control signal using the input signal;
a shifter circuit configured to generate a first shifted signal and a second shifted signal using the first control signal, the second control signal, and second power supply voltage level different than the first power supply voltage level; and
a selection circuit configured to select, using a value of a previous output signal and the second power supply voltage level, one of the first shifted signal or the second shifted signal to generate a current output signal.