US 11,923,812 B2
Delay-compensating power management integrated circuit
Nadim Khlat, Cugnaux (FR)
Assigned to Qorvo US, Inc., Greensboro, NC (US)
Filed by Qorvo US, Inc., Greensboro, NC (US)
Filed on May 27, 2021, as Appl. No. 17/331,739.
Claims priority of provisional application 63/064,773, filed on Aug. 12, 2020.
Prior Publication US 2022/0052655 A1, Feb. 17, 2022
Int. Cl. H03F 1/30 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01)
CPC H03F 3/195 (2013.01) [H03F 3/245 (2013.01); H03F 2200/102 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A power management integrated circuit (PMIC) comprising:
a target voltage circuit comprising:
an envelope detector circuit configured to detect a time-variant envelope of an analog signal, wherein the detected time-variant envelope is delayed from the time-variant envelope of the analog signal by a first temporal delay;
an analog look-up table (LUT) circuit configured to generate a target voltage based on the detected time-variant envelope of the analog signal, wherein the target voltage is delayed from the detected time-variant envelope of the analog signal by a second temporal delay; and
a voltage processing circuit configured to generate a modified target voltage that is time-adjusted relative to the time-variant envelope of the analog signal to thereby substantially offset at least the first temporal delay and the second temporal delay.