US 11,923,807 B2
Integrated circuit yield improvement
Parvez H. Daruwalla, San Diego, CA (US); Yucheng Tong, San Diego, CA (US); and Jonathan James Klaren, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on May 26, 2021, as Appl. No. 17/331,436.
Prior Publication US 2022/0385240 A1, Dec. 1, 2022
Int. Cl. H03F 1/22 (2006.01); G01R 31/28 (2006.01); H03F 3/195 (2006.01); H03F 3/24 (2006.01); H03F 3/72 (2006.01)
CPC H03F 1/223 (2013.01) [G01R 31/2834 (2013.01); H03F 3/195 (2013.01); H03F 3/245 (2013.01); H03F 3/72 (2013.01); H03F 2200/261 (2013.01); H03F 2200/294 (2013.01); H03F 2200/451 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit including:
(a) an active circuit including a first ground connection;
(b) a bias network coupled to the active circuit and including a second ground connection, the bias network configured to provide a calibrated bias voltage to the active circuit corresponding to a specified current for the active circuit; and
(c) a calibration switch coupled between the first ground connection and the second ground connection, the calibration switch configured to be closed during calibration of the active circuit and open after completion of calibration of the active circuit.